Raghavendra Jogina
Platform Debug Engineer at lanfest.intel.com
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Haim Aluf
VLSI Lab compute image and high level owner + HW image Development at Intel
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Sarah Baxter
Smart Storage Program Owner /F34 Globals Layout Coordinator at Intel
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Flavio Bergamaschi
Principal Engineer, Director and Chief Technology Officer Private AI and Analytics at Intel
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Tricia Stream
Director, Chief Executive Officer Executive Comms at Intel
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